1. Field of the Invention
The present invention relates to a method of production of a semiconductor device; and, more particularly relates to a method of production of a semiconductor device having a BiCMOS transistor.
2. Description of the Related Art
Along with the increasingly small size and lighter weight of electronic equipment and the reduction of power consumption in recent years, there has been growing demand for higher integration and greater miniaturization of semiconductor devices. Therefore, there has been development of a bipolar CMOS (Bi-CMOS) combining a CMOS having the characteristics of low power consumption and high integration and a bipolar transistor having the characteristics of a strong drive force and high speed.
FIG. 13 is a sectional view of a BiCMOS transistor produced by a method of production of the related art.
As shown in FIG. 13, an n-type epitaxial layer 2 is formed on a p-type semiconductor substrate 1, and an element isolation insulating film 3 is formed by a LOCOS technique on a surface of the n-type epitaxial layer 2.
In an npn bipolar transistor formation region, an n-type collector burying region 4 is formed below the n-type epitaxial layer 2 forming an n-type collector region, and a selective-ion-implantation-of-collector (SIC) region 17 for increasing the concentration of impurity directly below a base is formed above the n-type collector burying region 4.
An intrinsic base region 15 containing a p-type impurity and an external base region 16 for taking out a base containing a p-type impurity of a higher concentration than that in the intrinsic base region 15 and reduced in resistance are formed connected on the surface of the n-type epitaxial layer 2.
A silicon oxide film 33 is formed on the p-type base regions (15 and 16). Emitter polycrystalline silicon 24 is formed in an opening 33a formed in the silicon oxide film 33 and on the silicon oxide film 33. An n-type emitter region 25 is formed on the surface of the intrinsic base region 15 below the emitter polycrystalline silicon 24.
Also, an n-type collector plug region 6 and an n-type collector take-out region 6a are formed on a part of the n-type epitaxial layer 2 on the n-type collector burying region 4 over the p-type base regions (15 and 16).
An n-type isolation region 5 for isolation from the p-type semiconductor substrate 1 is formed on a pMOS transistor formation region. Further, an n-type well 7 is formed in the n-type epitaxial layer 2. Further, a p-type well 8 is formed in the nMOS transistor region.
In the pMOS and the nMOS transistor formation regions, source/drain regions (12 and 14) having LDD regions (11 and 13) are formed on the surfaces of the n-type well 7 and the p-type well 8, respectively.
Also, gate electrodes (22 and 23) are formed between the source/drain regions (12 and 14) via the gate oxide films (31a and 31b). Sidewall insulating films (32a and 32b) are formed on the side portions of the gate electrodes (22 and 23).
A silicon oxide film 33 is formed covering the entire surfaces of the gate electrodes (22 and 23). An interlayer insulating film 34 is formed covering the entire surfaces of the transistors, contact holes (41, 42, 43, 44, 45, 46, and 47) reaching the source/drain regions (12 and 14) of the pMOS and nMOS transistors, the external base region 16 and an emitter electrode 24 of the npn bipolar transistor. A collector take-out region 6a is formed in the silicon oxide film 33 and the interlayer insulating film 34. Interconnection layers (51, 52, 53, 54, 55, 56, and 57) are formed inside and over the contact holes.
An example of a method of production of the semiconductor device having the above configuration will be explained next.
First, as shown in FIG. 14A, for example, a p-type silicon semiconductor substrate 1 is oxidized by thermal oxidation to form an oxide film on the surface. On the upper surface of the oxide film, a resist film R1 of a pattern having openings at the npn bipolar transistor formation region and the pMOS transistor formation region on the above silicon semiconductor substrate 1 is formed by lithography.
Then, the oxide film is patterned by using the resist film R1 as a mask, so as to form an oxide film 36 having openings at the npn bipolar transistor formation region and the pMOS transistor formation region.
Next, as shown in FIG. 14B, the resist film R1 is removed and antimony is diffused in the silicon semiconductor substrate 1 through the openings formed in the above oxide film 36 by thermal diffusion using a solid source of antimony oxide (Sb2O3) so as to form, for example, an n-type collector burying region 4 and an n-type isolation region 5 for isolation from the p-type semiconductor substrate 1.
Next, as shown in FIG. 15C, the oxide film 36 is removed by, for example, wet etching, and then an n-type epitaxial layer 2 is formed on the silicon semiconductor substrate 1 by epitaxial growth.
Next, as shown in FIG. 15D, an element isolation insulating film 3 is formed on the n-type epitaxial layer 2 by a LOCOS process.
In the process of forming the element isolation insulating film 3, for example, a silicon oxide film 3a is formed by thermal oxidation on the surface of the n-type epitaxial layer 2, a not illustrated silicon nitride film is formed on regions other than the element isolation insulating film formation region on the silicon oxide film 3a and the surface of the n-type epitaxial layer 2 is thermally oxidized using the silicon nitride film as an oxidation resistant mask to form the element isolation insulating film 3. Then, the silicon nitride film is removed by etching.
Next, as shown in FIG. 16E, a resist film R2 having an opening at a region for forming an n-type collector plug region on the npn bipolar transistor formation region is formed. The resist film R2 is used as a mask and, for example, the n-type impurity phosphorus is implanted, so as to form an n-type collector plug region 6 connected to the n-type collector burying region 4 on the n-type epitaxial layer 2. Then, the resist film R2 is removed.
Next, as shown in FIG. 16F, a resist film R3 having an opening at the pMOS transistor formation region is formed by lithography on the n-type epitaxial layer 2. An n-type impurity, for example, phosphorus, is implanted to form an n-type well 7. Then, the resist film 3 is removed.
Next, as shown in FIG. 17G, a resist film R4 having openings at an nMOS transistor formation region and a part of the element isolation region between the nMOS and pMOS transistor and npn bipolar transistor formation regions is formed on the n-type epitaxial layer 2 by lithography. A p-type impurity boron is then, for example, implanted to form a p-type well using the element isolation region.
Next, as shown in FIG. 17H, the resist film R4 is removed. Then, the oxide film 3a is removed for example by wet etching, and a gate oxide film 31 is formed, for example, by thermal oxidation.
Next, as shown in FIG. 18I, gate electrodes (22 and 23) are formed on the nMOS and pMOS transistor formation regions.
Next, as shown in FIG. 18J, a resist film R5 having an opening at the pMOS formation region is formed by lithography. The resist film R5 is used as a mask for ion implantation of a p-type impurity, for example, boron difluoride (BF2+) to form a p-type LDD region 11 in the n-type wells 7 on the two sides of the gate electrode 22. Then the resist film R5 is removed.
Next, as shown in FIG. 19K, a resist film R6 having an opening at the nMOS transistor formation region is formed by lithography. The resist film R6 is used as a mask for implantation of an n-type impurity, for example, arsenic (As+) to form an n-type LDD region 13 in the p-type wells 8 on the two sides of the gate 23. Then, the resist film R6 is removed.
Next, as shown in FIG. 19L, a resist film R7 having an opening at the intrinsic base formation region of the npn bipolar transistor is formed by lithography. The resist film R7 is used as a mask for ion implantation of an n-type impurity, for example, boron difluoride to form an intrinsic base region 15.
Furthermore, by using the resist R7 as a mask for ion implantation of an n-type impurity of, for example, phosphorus, an SIC region 17 for increasing the concentration of the collector impurity immediately below the base is formed. Then, resist film R7 is removed.
Next, as shown in FIG. 20M, a sidewall insulating film 32 is formed by covering the transistors and depositing silicon oxide on the entire surface by CVD.
Next, as shown in FIG. 20N, the sidewall insulating film 32 is removed by etching, for example, by reactive ion etching (RIE) and the sidewall insulating films (32a and 32b) are formed on the side portions of the gate electrodes (22 and 23).
Then, as shown in FIG. 21O, a resist film R8 having openings at the nMOS transistor region and the collector take-out region of an npn bipolar transistor is formed by lithography. This is used as a mask for ion implantation of an n-type impurity of, for example, arsenic to form the source/drain region 14 of the nMOS transistor and the collector take-out region 6a of the npn bipolar transistor. Then, the resist film R8 is removed.
Next, as shown in FIG. 21P, a resist film R9 having openings at the pMOS transistor formation region and the external base formation region of the npn bipolar transistor is formed by lithography. This is used as a mask for ion implantation of a p-type impurity of, for example, boron difluoride to form a source/drain region 12 of the pMOS transistor and an external base region 16 of the npn bipolar transistor. Then, the resist film R9 is removed.
Next, as shown in FIG. 22Q, a silicon oxide film 33 is deposited on the entire surface, a resist film R10 having an opening at the emitter formation region is formed by lithography on the silicon oxide film 33, and the resist film R10 is used as a mask to form an emitter formation opening 33a in the silicon oxide film 33. Then, the resist film R10 is removed.
Next, as shown in FIG. 22R, an emitter polycrystalline silicon-use layer 24a doped with an n-type impurity arsenic to a high concentration for forming the emitter polycrystalline silicon is formed on the entire surface, including the inside of the opening 33a, by low pressure chemical vapor deposition (LPCVD).
Next, as shown in FIG. 23S, a resist film R11 having a pattern of the emitter polycrystalline silicon of the npn bipolar transistor is formed by lithography on the emitter polycrystalline silicon-use layer 24a. The resist film R11 is used as a mask for etching the emitter polycrystalline silicon-use layer 24a to form the emitter polycrystalline silicon 24. Then, the resist film R11 is removed.
Next, as shown in FIG. 23T, for example, rapid thermal annealing (RTA) is performed so as to activate the impurities introduced in the source/drain regions (12 and 14) of the pMOS and nMOS transistors. Also, by heat treatment, the impurities are diffused in the p-type intrinsic base region 15 via the opening 33a from the emitter polycrystalline silicon 24 to the silicon oxide film 33 to form an n-type emitter region 25.
After that, borophosphosilicate glass (BPSG) is deposited on the entire surface to form an interlayer insulating film 34.
A not shown resist film is formed on the interlayer insulating film 34. By using the resist film as a mask, openings (41 and 42) reaching the source/drain regions 12 of the pMOS transistor, openings (43 and 44) reaching the source/drain regions 14 of the nMOS transistor, an opening 45 reaching the external base region 16 of the npn bipolar transistor, an opening 46 reaching the emitter polycrystalline silicon 24, and an opening 47 reaching the collector take-out region 6a are formed in the interlayer insulating film 34 and the silicon oxide film 33.
In the processes thereafter, not shown tungsten plugs are formed by depositing tungsten inside the openings (41 to 47). Via the tungsten plugs, interconnections (51 and 52) connected to the source/drain regions 12 of the pMOS transistor, interconnections (53 and 54) connected to the source/drain regions 14 of the nMOS transistor, an interconnection 56 connected to the emitter polycrystalline silicon 24, and an interconnection 57 connected to the collector take-out region 6a are formed so as to obtain the semiconductor device shown in FIG. 13.
In the method of production of a semiconductor device having a BiCMOS according to the above related art, as shown in FIG. 20N, the sidewall insulating films (32a and 32b) of the nMOS and pMOS transistors are formed by removing the sidewall insulating films 32 by RIE. At this time, since the silicon portion (epitaxial layer 2) is exposed at other than regions of the element isolation insulating film 32 and regions of the gate electrodes (22 and 23), the silicon portion is damaged by the RIE.
At the pMOS and nMOS transistor formation regions, at the time of forming the sidewall insulating film, the silicon portion is exposed at the source/drain regions. Since the source/drain regions are regions where highly concentrated impurities are introduced, the effect due to the exposure of the silicon portion is small.
However, in the bipolar transistor formation region, since the emitter region is formed at the region where the silicon portion is exposed, there is the disadvantage that the reliability declines due to a reduction of the current amplification factor hFE at a low current along with an increase of the surface recombination current.
The decrease of the hFE at a low current due to an increase of the surface recombination current on the bipolar transistor region is generally known. The surface recombination current is caused by the recombination of carriers via a surface energy level generated by crystal discontinuity on the substrate surface and other defects; thus, it is considerably affected by the processing state of the surface.
Accordingly, it is important that no RIE damage occur in the emitter formation region for forming the active region of the bipolar transistor and between the emitter and the p-type external base region.
Also, in the related art, as shown in FIG. 22Q, in the process for forming an opening in the silicon oxide film 33 by the resist film RIO in order to form emitter polycrystalline silicon, it is necessary to consider the alignment of the opening 33a for formation of the emitter region 25 with the external base regions 16 on the left and the right.
Namely, when the distance between the emitter region 25 and the external base regions 16 is too short, there are the disadvantages of a decline of voltage resistance and an increase of the junction capacity of the emitter region 25 and the intrinsic and external base regions (15 and 16), while when the distance between the emitter region 25 and the external base regions 16 is too long, an increase of base resistance and other disadvantages are caused. Therefore, optimization of the distance between the emitter region 25 and the external base regions 16 becomes important.
Considering the above disadvantages and the deviation in positioning of the resist film, to secure a certain margin of safety the distance between the emitter region 25 and the external base region 16 is normally made relatively large.
Specifically, for example, in the process for protecting the emitter polycrystalline silicon formation region in FIG. 21P with the resist film R9 and forming the external base region 16, the resist film R9 of the part for protecting the emitter polycrystalline silicon formation region is formed wide, the resist film R10 is positioned with respect to the widely protected region in the process from FIG. 22 on, and the emitter polycrystalline silicon is formed. Since the distance between the emitter region 25 and the external base region 16 becomes relatively large due to the need for this margin, there is a limit to miniaturization of the BiCMOS.
An object of the present invention is to provide a method of production of a semiconductor device able to be miniaturized by preventing the decline of the hog at a low current caused by an increase of a surface recombination current of the bipolar transistor and forming the external base region by self-alignment with respect to emitter polycrystalline silicon in a BiCMOS process.
To attain the above object, according to the present invention, there is provided a method of production of a semiconductor device forming a first semiconductor element comprising a collector region, an emitter region, and an intrinsic base region on a first region and forming a second semiconductor element comprising source/drain regions and a gate electrode on a second region and a sidewall insulating film on side portions of the gate electrode, including the steps of: forming said collector region on a semiconductor substrate of said first region; forming said gate electrode on a semiconductor substrate of said second region; forming said intrinsic base region on said semiconductor substrate of said first region; forming an insulating film having an opening at an emitter formation region on said intrinsic base region over said semiconductor substrate of said first and second regions; forming an emitter electrode in said opening and near said opening of said insulating film of said first region; forming a protective film for suppressing introduction of impurities to said emitter electrode of said first region; removing said insulating film of said first and second regions while leaving a sidewall insulating film on said gate electrode side portions and emitter region formation insulating film on a part under said emitter electrode by using said emitter electrode as a mask; forming an external base region connected to said intrinsic base region by self-alignment with respect to said emitter electrode over said semiconductor substrate of said first region; forming said source/drain regions on said semiconductor substrate of said second region by using said sidewall insulating film as a mask; and, forming said emitter region connected to said intrinsic base region on said semiconductor substrate of said first region under said opening by diffusing an impurity in said intrinsic base region from said emitter electrode via said opening of said emitter region formation insulating film.
According to the above method, an intrinsic base region is formed, an insulating film having an opening at an emitter formation region on the intrinsic base region is formed, an emitter electrode of a first semiconductor element is formed and a protective film is formed on the insulating film having the opening.
Next, a sidewall insulating film is left on the gate electrode side portion by using the emitter electrode as a mask: and, the insulating films on the first and second regions are removed while leaving the emitter region formation insulating film partially below the emitter electrode.
Next, an external base region connected to the intrinsic base region is formed by self-alignment with respect to the emitter electrode on the semiconductor substrate on the first region.
Accordingly, at the time of forming the sidewall insulating film, since the emitter region formation insulating film below the emitter electrode is left, the sidewall insulating film can be formed on the emitter region as an active region of the first semiconductor element and the semiconductor substrate between the emitter region and the external base region without any damage.
Also, since the external base region can be formed by self-alignment with respect to the emitter electrode, and since a protective film is formed over the emitter electrode, it is possible to prevent changes in the characteristic caused by the introduction of impurities for forming the external base region to the emitter electrode.
Also, preferably, the step of forming said intrinsic base region comprises forming said intrinsic base region by ion implantation of an impurity to said semiconductor substrate in said first region and forming a diffusion layer of a conductive impurity at a lower concentration than that of a conductive impurity contained in said source/drain regions on said semiconductor substrate of said gate electrode side portion by ion implantation of an impurity to said second region.
As a result, it is possible to form a low concentration diffusion layer of the second semiconductor element simultaneously in the step of forming an intrinsic base region of the first semiconductor element, so the production steps can be reduced.
Preferably, the method comprises forming an impurity layer for increasing the impurity concentration of said collector region under said intrinsic base region in said first region after the process of forming said intrinsic base region and before forming said insulating film and forming a pocket region containing a conductive impurity different from the low concentration diffusion layer under said low concentration diffusion layer in said second region in the step of forming the impurity layer.
As a result, for example, in the step of forming an impurity layer for increasing the impurity concentration in the collector region below the base region of the first semiconductor element, a pocket region for preventing short channel effects of the second semiconductor element can be formed simultaneously, so the production steps can be reduced.
Preferably, the step of forming said external base region comprises ion implantation of an impurity to said semiconductor substrate in said first region and forming said external base region by self-alignment with respect to said emitter electrode while suppressing implantation of impurities to said emitter electrode by said protective film.
As a result, the source/drain regions of the second semiconductor element can be formed simultaneously in the step of forming the external base region of the first semiconductor element, so the production steps can be reduced.
For example, the step of forming said emitter electrode and the step of forming said protective film includes the steps of: forming an emitter-use conductive layer inside said opening of said insulating film and on said insulating film; forming said protective film on said emitter-use conductive layer; and, forming said emitter electrode and said protective film by forming a mask layer on said protective film-use film of a region where said emitter region is to be formed and removing said emitter-use conductive layer and said protective film-use film by using the mask layer as a mask.